� ��TR8N�(jN�!,Rockchip RK3228 Evaluation board$2rockchip,rk3228-evbrockchip,rk3228aliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu2arm,cortex-a7fjq���@��psci�cpu@f01Zcpu2arm,cortex-a7fjq��psci�cpu@f02Zcpu2arm,cortex-a7fjq��psci�cpu@f03Zcpu2arm,cortex-a7fjq��psci�opp_table02operating-points-v2��opp-408000000�Q��~���@�opp-600000000�#�F���opp-816000000�0�,�B@opp-1008000000�<����opp-1200000000�G���txbus 2simple-bus�pdma@110f00002arm,pl330arm,primecellf@�� 0apb_pclk� arm-pmu2arm,cortex-a7-pmu0LMNO<psci2arm,psci-1.0arm,psci-0.2�smctimer2arm,armv7-timerO0   sn6oscillator 2fixed-clocksn6�xin24m��display-subsystem2rockchip,display-subsystem�i2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ 0i2s_clki2s_hclk�Q��  �txrx�default�  �disabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ 0i2s_clki2s_hclk�P�� �txrx �disabledspdif@100d00002rockchip,rk3228-spdiff  �S� 0mclkhclk� �tx�default�  �disabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf@ 0i2s_clki2s_hclk�R�� �txrx �disabledsyscon@11000000&2rockchip,rk3228-grfsysconsimple-mfdf�io-domains"2rockchip,rk3228-io-voltage-domain �disabledusb2-phy@7602rockchip,rk3228-usb2phyf` ��0phyclk �usb480m_phy0� �disabled�6otg-port$;<=�otg-bvalidotg-idlinestate� �disabled�5host-port > �linestate� �disabled�7usb2-phy@8002rockchip,rk3228-usb2phyf ��0phyclk �usb480m_phy1� �disabled�8otg-port D �linestate� �disabled�9host-port E �linestate� �disabled�:serial@110100002snps,dw-apb-uartf 7sn6�MU0baudclkapb_pclk�default � �� �disabledserial@110200002snps,dw-apb-uartf 8sn6�NV0baudclkapb_pclk�default��� �disabledserial@110300002snps,dw-apb-uartf 9sn6�OW0baudclkapb_pclk�default����okayefuse@110400002rockchip,rk3228-efusef �G 0pclk_efuseid@7fcpu_leakage@17fi2c@110500002rockchip,rk3228-i2cf $0i2c�L�default� �disabledi2c@110600002rockchip,rk3228-i2cf %0i2c�M�default� �disabledi2c@110700002rockchip,rk3228-i2cf &0i2c�N�default� �disabledi2c@110800002rockchip,rk3228-i2cf '0i2c�O�default� �disabledspi@110900002rockchip,rk3228-spif  1�AR0spiclkapb_pclk�default� �disabledwatchdog@110a0000 2snps,dw-wdtf  (�b �disabledpwm@110b00002rockchip,rk3288-pwmf  �^0pwm�default� �disabledpwm@110b00102rockchip,rk3288-pwmf  �^0pwm�default� �disabledpwm@110b00202rockchip,rk3288-pwmf  �^0pwm�default� �disabledpwm@110b00302rockchip,rk3288-pwmf 0 �^0pwm�default� �disabledtimer@110c0000,2rockchip,rk3228-timerrockchip,rk3288-timerf  + �a 0timerpclkclock-controller@110e00002rockchip,rk3228-cruf�!H.��k��b$>#g��0�,�e�р�рxh��р�рxh��thermal-zonescpu-thermalSdi�w tripscpu_alert0�p��apassive�!cpu_alert1�$���apassive�"cpu_crit�_��� acriticalcooling-mapsmap0�!0�����������������map1�"0���������������������������������tsadc@111500002rockchip,rk3228-tsadcf :�HX0tsadcapb_pclk.H>�jW �tsadc-apb�initdefaultsleep�#�$�#��s�okay�� hdmi-phy@120300002rockchip,rk3228-hdmi-phyf�m�0sysclkrefoclkrefpclk� �hdmiphy_phy� �disabled�'gpu@20000000"2rockchip,rk3228-maliarm,mali-400f H�gpgpmmupp0ppmmu0pp1ppmmu1��� 0buscorej~ �disablediommu@200208002rockchip,iommuf   ��� 0aclkiface1 �disablediommu@200304802rockchip,iommuf �@ �@ ��� 0aclkiface1 �disabledvop@200500002rockchip,rk3228-vopf �  ����0aclk_vopdclk_vophclk_vopjdef �axiahbdclk>% �disabledport�endpoint@0fE&�+iommu@20053f002rockchip,iommuf ?  ��� 0aclkiface1 �disabled�%rga@20060000(2rockchip,rk3228-rgarockchip,rk3288-rgaf  !����0aclkhclksclkjkmn �coreaxiahbiommu@200708002rockchip,iommuf  ��� 0aclkiface1 �disabledhdmi@200a00002rockchip,rk3228-dw-hdmif � #.�U'�l{�0iahbisfrcec�default �()*j`�hdmil'qhdmi �disabledportsportendpoint@0fE+�&mmc@3000000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   ��Drv0biuciuciu-driveciu-sample{�default �,-. �disabledmmc@3001000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   ��Esw0biuciuciu-driveciu-sample{�default �/01 �disabledmmc@3002000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ s<4`�<4` ��Guy0biuciuciu-driveciu-sample���{�default �234jS�reset�okay����usb@3004000022rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 ��0otg�otg���@ l5 qusb2-phy �disabledusb@30080000 2generic-ehcif0  ��6l7qusb �disabledusb@300a0000 2generic-ohcif0   ��6l7qusb �disabledusb@300c0000 2generic-ehcif0   ��8l9qusb �disabledusb@300e0000 2generic-ohcif0  ��8l9qusb �disabledusb@30100000 2generic-ehcif0 B ��8l:qusb �disabledusb@30120000 2generic-ohcif0 C ��8l:qusb �disabledethernet@302000002rockchip,rk3228-gmacf0  �macirq8�~����oM0stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 �stmmaceth�okay.|>���,output9;DrmiiM<mdio2snps,dwmac-mdioethernet-phy@042ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22f��j?X�<interrupt-controller@32010000 2arm,gic-400j f22 2@ 2`   �pinctrl2rockchip,rk3228-pinctrl�gpio0@111100002rockchip,gpio-bankf 3�@��jgpio1@111200002rockchip,gpio-bankf 4�A��jgpio2@111300002rockchip,gpio-bankf 5�B��jgpio3@111400002rockchip,gpio-bankf 6�C��jpcfg-pull-up��@pcfg-pull-down��?pcfg-pull-none��>pcfg-pull-none-drv-12ma� �=sdmmcsdmmc-clk�=�,sdmmc-cmd�=�-sdmmc-bus4@�====�.sdiosdio-clk�=�/sdio-cmd�=�0sdio-bus4@�====�1emmcemmc-clk�>�2emmc-cmd�>�3emmc-bus8��>>>>>>>>�4gmacrgmii-pins��> >>==== = =>>>> >>rmii-pins��> >>== =>>>>phy-pins �>>hdmihdmi-hpd�?�)hdmii2c-xfer �>>�(hdmi-cec�>�*i2c0i2c0-xfer �>>�i2c1i2c1-xfer �>>�i2c2i2c2-xfer �>>�i2c3i2c3-xfer �>>�spi0spi0-clk� @�spi0-cs0�@�spi0-tx� @�spi0-rx� @�spi0-cs1� @�spi1spi1-clk�@spi1-cs0�@spi1-rx�@spi1-tx�@spi1-cs1�@i2s1i2s1-bus��> > > > >>>>>� pwm0pwm0-pin�>�pwm1pwm1-pin�>�pwm2pwm2-pin� >�pwm3pwm3-pin� >�spdifspdif-tx�>� tsadcotp-pin�>�#otp-out�>�$uart0uart0-xfer �>>� uart0-cts�>� uart0-rts�>�uart1uart1-xfer � > >�uart1-cts�>uart1-rts� >uart2uart2-xfer �@>�uart21-xfer � @ >uart2-cts�>uart2-rts�>memory@60000000Zmemoryf`@vcc-phy-regulator2regulator-fixed�vcc_phyw@,w@DX�; #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsarm,pl330-periph-burstclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsdmasdma-namespinctrl-namespinctrl-0statusinterrupt-names#phy-cellsreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarity#iommu-cellsiommusremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-supplyphy-modephy-handlephy-is-integratedinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on