� ����8� ( l��:engicam,px30-core-ctouch2engicam,px30-corerockchip,px30 +7Engicam PX30.Core C.TOUCH 2.0aliases=/ethernet@ff360000G/i2c@ff180000L/i2c@ff190000Q/i2c@ff1a0000V/i2c@ff1b0000[/serial@ff030000c/serial@ff158000k/serial@ff160000s/serial@ff168000{/serial@ff170000�/serial@ff178000�/spi@ff1d0000�/spi@ff1d8000�/mmc@ff370000�/mmc@ff380000�/mmc@ff390000cpus+cpu@0�cpuarm,cortex-a35��psci����Z!cpu@1�cpuarm,cortex-a35��psci����Z!cpu@2�cpuarm,cortex-a35��psci����Z! cpu@3�cpuarm,cortex-a35��psci����Z! idle-states)pscicpu-sleeparm,idle-state6G^xo��!cluster-sleeparm,idle-state6G^�o��!opp-table-0operating-points-v2�!opp-600000000�#�F �~�~��p��@�opp-816000000�0�, ����p��@opp-1008000000�<� ������p��@opp-1200000000�G�� �� � �p��@opp-1296000000�M?d ��p�p�p��@arm-pmuarm,cortex-a35-pmu0�defg� display-subsystemrockchip,display-subsystem�  �disabledexternal-gmac-clock fixed-clock���� gmac_clkinpsci arm,psci-1.0�smctimerarm,armv8-timer0�   thermal-zonessoc-thermal(>�L�^ tripstrip-point-0npz��passivetrip-point-1nLz��passive!soc-critn�8z� �criticalcooling-mapsmap0� ����������map1� ����������gpu-thermal(d>�^ xin24m fixed-clock�n6xin24m!kpower-management@ff000000$rockchip,px30-pmusysconsimple-mfd��power-controllerrockchip,px30-power-controller�+!mpower-domain@5��<��power-domain@7���;��power-domain@9�  ��C@?��power-domain@10� @���978:��power-domain@11� ���K��power-domain@12� X���������D56��power-domain@13� (�����3� !"�power-domain@14��I�#�syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd��+!�io-domains$rockchip,px30-pmu-io-voltage-domain�okay�$�$reboot-modesyscon-reboot-mode��RB��RB� RB�RB�RB�serial@ff030000$rockchip,px30-uartsnps,dw-apb-uart�� ��%%(baudclkapb_pclk4&&9txrxCMZdefault h'() �disabledi2s@ff060000rockchip,px30-i2s-tdm�� � �(mclk_txmclk_rxhclk4&&9txrxr*�� �tx-mrx-mZdefault0h+,-./0123456� �disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s�� � �(i2s_clki2s_hclk4&&9txrxZdefaulth789:� �disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s�� ��(i2s_clki2s_hclk4&&9txrxZdefaulth;<=>� �disabledinterrupt-controller@ff131000 arm,gic-400��@��� �@ �`  � !syscon@ff140000$rockchip,px30-grfsysconsimple-mfd��+!*io-domains rockchip,px30-io-voltage-domain�okay�$�$�$�$$?lvdsrockchip,px30-lvds@"dphyr*,lvds �disabledports+port@0�+endpoint@0�<A!�endpoint@1�<B!�serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart��� ��I(baudclkapb_pclk4&&9txrxCMZdefault hCDE �disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart�� ��J(baudclkapb_pclk4&&9txrxCMZdefaulthF�okayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart��� ��K(baudclkapb_pclk4&&9txrxCMZdefault hGHI �disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart�� ��L(baudclkapb_pclk4&& 9txrxCMZdefault hJKL �disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart��� ��M(baudclkapb_pclk4& & 9txrxCMZdefault hMNO �disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2c���N (i2cpclk �ZdefaulthP+�okaypmic@20rockchip,rk809�  Q�ZdefaulthRLmrk808-clkout1rk808-clkout2{S�S�S�S�T�T�T�T�SregulatorsDCDC_REG1�vdd_log� ~�4�pLqregulator-state-memay~�DCDC_REG2�vdd_arm� ~�4�pLq!regulator-state-mem�y~�DCDC_REG3�vcc_ddr� regulator-state-memaDCDC_REG4�vcc_3v3� 2Z�42Z�!$regulator-state-memay2Z�DCDC_REG5 �vcc3v3_sys� 2Z�42Z�!Tregulator-state-memay2Z�LDO_REG1�vcc_1v0� B@4B@regulator-state-memayB@LDO_REG2�vcc_1v8� w@4w@!?regulator-state-memayw@LDO_REG3�vdd_1v0� B@4B@regulator-state-memayB@LDO_REG4 �vcc3v0_pmu� 2Z�42Z�regulator-state-memay2Z�LDO_REG5 �vccio_sd� w@42Z�regulator-state-memay2Z�SWITCH_REG1  �vcc3v3_lcdSWITCH_REG2 �vcc5v0_host� i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2c���O (i2cpclk �ZdefaulthU+ �disabledi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2c���P (i2cpclk � ZdefaulthV+ �disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c��� Q (i2cpclk � ZdefaulthW+ �disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi�� ��$U(spiclkapb_pclk4& & 9txrxZdefaulthXYZ[+ �disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi��� ��%V(spiclkapb_pclk4&&9txrxZdefaulth\]^_`+ �disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt���[ �% �disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm�� �"S (pwmpclkZdefaultha��okaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm�� �"S (pwmpclkZdefaulthb� �disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm�� �"S (pwmpclkZdefaulthc� �disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm�� 0�"S (pwmpclkZdefaulthd� �disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm�� ��#T (pwmpclkZdefaulthe� �disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm�� ��#T (pwmpclkZdefaulthf� �disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm�� � �#T (pwmpclkZdefaulthg� �disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm�� �0�#T (pwmpclkZdefaulthh� �disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer��! ��Y& (pclktimerdma-controller@ff240000arm,pl330arm,primecell��$@���� (apb_pclk�!&tsadc@ff280000rockchip,px30-tsadc��( �$�,��P�,X(tsadcapb_pclk� �tsadc-apbr*��Zinitdefaultsleephij!i+�okayAX! saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc��(� �Ts�-W(saradcapb_pclk� �saradc-apb �disablednvmem@ff290000rockchip,px30-otp��)@�/Za(otpapb_pclkphy��phy+id@7�cpu-leakage@17�performance@1e��clock-controller@ff2b0000rockchip,px30-cru��+ �k% (xin24mgpllr*�8�����@I�F�q �� ���р�р�� ��!clock-controller@ff2bc000rockchip,px30-pmucru��+��k(xin24mr*��%%% �G�������!%syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd��,+usb2phy@100rockchip,px30-usb2phy� �% (phyclk��l usb480m_phy�okay!lhost-port� �D �linestate�okay!ootg-port�$�BA@�otg-bvalidotg-idlinestate�okay!nphy@ff2e0000rockchip,px30-dsi-dphy��.�% E (refpclk>�apb��m  �disabled!@phy@ff2f0000rockchip,px30-csi-dphy��/@�F(pclk��m /�apbr* �disabled!�usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc2��0 �>�(otg�otg����@ n "usb2-phy�m�okayusb@ff340000 generic-ehci��4 �<�o"usb�m�okayusb@ff350000 generic-ohci��5 �=�o"usb�m�okayethernet@ff360000rockchip,px30-gmac��6 �+�macirq@�>??@A�CL[(stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedr*rmiiZdefaulthpq�m ^ �stmmaceth�okayoutput%$0 F�P�P [r mmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc��7@ �6 ��;CD(biuciuciu-driveciu-sampleku��рZdefaulthstuv�m�okay�� �$�$mmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc��8@ �7 ��8EF(biuciuciu-driveciu-sampleku��рZdefault hwxy�m �okay+��������z�wifi@1brcm,bcm4329-fmac�mmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc��9@ �5 �9GH(biuciuciu-driveciu-sampleku��рZdefault h{|}�m �okay&�spi@ff3a0000 rockchip,sfc��:@ �8�:(clk_sfchclk_sfc h~�Zdefault�m  �disablednand-controller@ff3b0000rockchip,px30-nfc��;@ �9��7(ahbnfc�7��рZdefault h���������m  �disabledopp-table-1operating-points-v2!�opp-200000000� ���~�opp-300000000�����opp-400000000�ׄ��opp-480000000��8�*�gpu@ff400000$rockchip,px30-maliarm,mali-bifrost��@@$�/.- �jobmmugpu�I��m� �disabled!video-codec@ff442000rockchip,px30-vpu��D �PO �vepuvdpu��� (aclkhclk5��m iommu@ff442800rockchip,iommu��D( �Q��� (aclkiface<�m !�dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsi��E �K�D(pclk@"dphy�m =�apbr*+ �disabledports+port@0�+endpoint@0�<�!�endpoint@1�<�!�vop@ff460000rockchip,px30-vop-big��F� �M����(aclk_vopdclk_vophclk_vop345 �axiahbdclk5��m  �disabledport+! endpoint@0�<�!�endpoint@1�<�!Aiommu@ff460f00rockchip,iommu��F �M��� (aclkiface�m < �disabled!�vop@ff470000rockchip,px30-vop-lit��G� �N����(aclk_vopdclk_vophclk_vop789 �axiahbdclk5��m  �disabledport+! endpoint@0�<�!�endpoint@1�<�!Biommu@ff470f00rockchip,iommu��G �N��� (aclkiface�m < �disabled!�isp@ff4a0000rockchip,px30-cif-isp��J�$�FIJ �ispmimipi �3��_(ispaclkhclkpclk5��"dphy�m  �disabledports+port@0�+iommu@ff4a8000rockchip,iommu��J� �F��� (aclkiface�m I<!�qos@ff518000rockchip,px30-qossyscon��Q� !qos@ff520000rockchip,px30-qossyscon��R !#qos@ff52c000rockchip,px30-qossyscon��R� !qos@ff538000rockchip,px30-qossyscon��S� !qos@ff538080rockchip,px30-qossyscon��S�� !qos@ff538100rockchip,px30-qossyscon��S� !qos@ff538180rockchip,px30-qossyscon��S�� !qos@ff540000rockchip,px30-qossyscon��T !qos@ff540080rockchip,px30-qossyscon��T� !qos@ff548000rockchip,px30-qossyscon��T� !qos@ff548080rockchip,px30-qossyscon��T�� !qos@ff548100rockchip,px30-qossyscon��T� ! qos@ff548180rockchip,px30-qossyscon��T�� !!qos@ff548200rockchip,px30-qossyscon��T� !"qos@ff550000rockchip,px30-qossyscon��U !qos@ff550080rockchip,px30-qossyscon��U� !qos@ff550100rockchip,px30-qossyscon��U !qos@ff550180rockchip,px30-qossyscon��U� !qos@ff558000rockchip,px30-qossyscon��U� !qos@ff558080rockchip,px30-qossyscon��U�� !pinctrlrockchip,px30-pinctrlr*d�+qgpio@ff040000rockchip,gpio-bank�� ��%x���!Qgpio@ff250000rockchip,gpio-bank��% ��\x���!�gpio@ff260000rockchip,gpio-bank��& ��]x���!rgpio@ff270000rockchip,gpio-bank��' ��^x���pcfg-pull-up�!�pcfg-pull-down�pcfg-pull-none�!�pcfg-pull-none-2ma��pcfg-pull-up-2ma��pcfg-pull-up-4ma��!�pcfg-pull-none-4ma��pcfg-pull-down-4ma��pcfg-pull-none-8ma��!�pcfg-pull-up-8ma��!�pcfg-pull-none-12ma�� !�pcfg-pull-up-12ma�� !�pcfg-pull-none-smt��!�pcfg-output-high�pcfg-output-low�pcfg-input-high��!�pcfg-input�i2c0i2c0-xfer � �!Pi2c1i2c1-xfer ��!Ui2c2i2c2-xfer ��!Vi2c3i2c3-xfer  � �!Wtsadctsadc-otp-pin �!itsadc-otp-out �!juart0uart0-xfer  � �!'uart0-cts  �!(uart0-rts  �!)uart1uart1-xfer ��!Cuart1-cts �!Duart1-rts �!Euart2-m0uart2m0-xfer ��uart2-m1uart2m1-xfer  ��!Fuart3-m0uart3m0-xfer ��uart3m0-cts �uart3m0-rts �uart3-m1uart3m1-xfer ��!Guart3m1-cts  �!Huart3m1-rts  �!Iuart4uart4-xfer ��!Juart4-cts �!Kuart4-rts �!Luart5uart5-xfer ��!Muart5-cts �!Nuart5-rts �!Ospi0spi0-clk �!Xspi0-csn �!Yspi0-miso  �!Zspi0-mosi  �![spi0-clk-hs �spi0-miso-hs  �spi0-mosi-hs  �spi1spi1-clk �!\spi1-csn0  �!]spi1-csn1  �!^spi1-miso �!_spi1-mosi  �!`spi1-clk-hs �spi1-miso-hs �spi1-mosi-hs  �pdmpdm-clk0m0 �pdm-clk0m1 �pdm-clk1 �pdm-sdi0m0 �pdm-sdi0m1 �pdm-sdi1 �pdm-sdi2 �pdm-sdi3 �pdm-clk0m0-sleep �pdm-clk0m1-sleep �pdm-clk1-sleep �pdm-sdi0m0-sleep �pdm-sdi0m1-sleep �pdm-sdi1-sleep �pdm-sdi2-sleep �pdm-sdi3-sleep �i2s0i2s0-8ch-mclk �i2s0-8ch-sclktx �!+i2s0-8ch-sclkrx  �!,i2s0-8ch-lrcktx �!-i2s0-8ch-lrckrx  �!.i2s0-8ch-sdo0 �!/i2s0-8ch-sdo1 �!1i2s0-8ch-sdo2 �!3i2s0-8ch-sdo3 �!5i2s0-8ch-sdi0 �!0i2s0-8ch-sdi1  �!2i2s0-8ch-sdi2  �!4i2s0-8ch-sdi3 �!6i2s1i2s1-2ch-mclk �i2s1-2ch-sclk �!7i2s1-2ch-lrck �!8i2s1-2ch-sdi �!9i2s1-2ch-sdo �!:i2s2i2s2-2ch-mclk �i2s2-2ch-sclk �!;i2s2-2ch-lrck �!<i2s2-2ch-sdi �!=i2s2-2ch-sdo �!>sdmmcsdmmc-clk �!ssdmmc-cmd �!tsdmmc-det �!usdmmc-bus1 �sdmmc-bus4@ ����!vsdiosdio-clk �!ysdio-cmd �!xsdio-bus4@ ����!wemmcemmc-clk  �!{emmc-cmd  �!|emmc-rstnout  �emmc-bus1 �emmc-bus4@ ����emmc-bus8� ��������!}flashflash-cs0 �!�flash-rdy  �!�flash-dqs  �!�flash-ale  �!�flash-cle  �!�flash-wrn  �!�flash-csl �flash-rdn �!�flash-bus8� ��������!�sfcsfc-bus4@ ����!�sfc-bus2 ��sfc-cs0 �!sfc-clk  �!~lcdclcdc-rgb-dclk-pin �lcdc-rgb-m0-hsync-pin �lcdc-rgb-m0-vsync-pin �lcdc-rgb-m0-den-pin �lcdc-rgb888-m0-data-pins� ���� � � ���� � �������������lcdc-rgb666-m0-data-pins ���� � � ���� � �������lcdc-rgb565-m0-data-pins ���� � � ���� � �����lcdc-rgb888-m1-data-pins �� � � �������������lcdc-rgb666-m1-data-pins� �� � � �������lcdc-rgb565-m1-data-pins� �� � � �����pwm0pwm0-pin �!apwm1pwm1-pin �!bpwm2pwm2-pin  �!cpwm3pwm3-pin �!dpwm4pwm4-pin �!epwm5pwm5-pin �!fpwm6pwm6-pin �!gpwm7pwm7-pin �!hgmacrmii-pins� �������� �!pmac-refclk-12ma  �!qmac-refclk  �cif-m0cif-clkout-m0  �dvp-d2d9-m0� ��������� � � �dvp-d0d1-m0  ��d10-d11-m0 ��cif-m1cif-clkout-m1 �dvp-d2d9-m1� ���� � �������dvp-d0d1-m1 ��d10-d11-m1 ��ispisp-prelight �btbt-enable-h �!�sdio-pwrseqwifi-enable-h �!�pmicpmic_int �!Rvcc5v0-sysregulator-fixed �vcc5v0_sys� LK@4LK@!Ssdio-pwrseqmmc-pwrseq-simple�� (ext_clock PZdefaulth� *�!zvcc3v3-btregregulator-gpio 6Zdefaulth��btreg-gpio-supply2Z�42Z���2Z� I�vcc3v3-rf-aux-modregulator-fixed�vcc3v3_rf_aux_mod2Z�42Z��  USxin32k fixed-clock��xin32k!�chosen `serial2:115200n8 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc1mmc2mmc0device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,outputremote-endpointrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspend#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsbits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiobus-widthfifo-depthmax-frequencycap-sd-highspeedcard-detect-delayvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104cap-mmc-highspeedmmc-hs200-1_8viommus#iommu-cellsrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinspost-power-on-delay-msreset-gpiosenable-active-highenable-gpiovin-supplystdout-path