This example intends to illustrate the false branches detection mechanism included in Yagle. A shifter is the typical design leading to the construction of false branches. This example is limited to 3 bits, but it is already possible to see that a simple depth-first search leads to the construction of a large number of branches having a large number of transistors.
In this example, we are going to study the behavior of Yagle on two shifters: a 4-bit shifter and a 32-bit shifter.
As previously explained , Yagle performs a functional analysis of the logical context. This functional analysis establishes the correlations between the transistors of the branches under construction. Yagle is then able to orient the transistors and to detect false branches.
It is possible to control the depth of the functional analysis with the yagleAnalysisDepth variable. In default configuration, the depth is 7. This depth is sufficient to perform the functional abstraction of most of the chips, in particular the present shifters:
> run.tcl |
The functional abstractions last a few seconds. We are now going to study the effects of lowering the depth of the analysis on the 4-bit shifter. Reducing the depth to 6 still leads to a correct abstraction, but reducing the depth to 5 leads to the construction of some false branches. To study the VHDL generated with a functional analysis depth of 5, set the yagleAnalysisDepth variable to 5 and run the Tcl script.
We can see that the VHDL generated with a depth of 5 has more complicated expressions than the VHDL generated with a depth of 6 and more. These expressions are the result of false branches and actually, this VHDL is not functional. With a depth less than 5, they are a huge number of false branches. The research is only stopped by a security mechanism avoiding combinational explosion (actually the maximum length of a branch).