This example presents how HITAS performs timing checks upon a sequential design. The example given here is a simple master-slave flip-flop (msdp2_y diagram below). It takes place in the directory ms/
Static Timing Analysis is performed by propagating interface constraints towards latch's inputs and commands, and towards output connectors. Once interface constraints have been propagated, the tool computes the setup and hold slacks.
The complete configuration required for database construction takes place in the db.tcl. It does not differ from previous examples
The complete configuration required for STA takes place in the sta.tcl.
Timing constraints are set in SDC format (Synopsys Design Constraints). Let's review the constraints commands applied to the flip-flop:
inf_SetFigureName msdp2_y | |
tells the tool to apply the SDC constraints to the design msdp2_y. | |
create_clock -period 1000 -waveform {500 0} ck | |
Defines the clock waveform. | |
set_input_delay -clock -ck -clock_fall -min 200 di | |
set_input_delay -clock -ck -clock_fall -max 300 di | |
Tells the tool that inputs signals on di may switch between times 200 and 300. | |
set_output_delay -clock ck -clock_fall -min 200 t | |
set_output_delay -clock ck -clock_fall -max 400 t | |
Tells the tool that the delay from output connector t to the next memory element (hypothetical). |
Launch of the STA is done by invoking the following commands (file sta.tcl):
The command:
set fig [ttv_LoadSpecifiedTimingFigure msdp2_y] |
reads the timing database from disk.
The command:
set stbfig [stb $fig] |
launches the static timing analysis. The stb function returns a pointer on the newly created figure, which back-annotates the timing database with timing propagation information.
The function:
stb_DisplaySlackReport [fopen slack.rep w] $fig * * ?? 10 all 10000 |
displays a global slack report in the file slack.rep.
The next sections explain how timing checks are performed. They describe the more common situations one can be faced to, i.e.:
For each situation, an example of slack report is shown, and we explain the details of the timing checks calculation.
Regarding input specifications, the STA engine of HITAS makes the assumption that input data is coming from a latch clocked on the opposite phase of the one the data arrives on. In our flip-flop example, dff_m is opened on the high state of ck, so di is supposed to come from a latch opened on the low state of ck.
As a result, di should be specified as coming from ck falling, i.e. when the latch src opens. The corresponding SDC commands should look like:
create_clock -period 1000 -waveform {500 0} ck set_input_delay -clock -ck -clock_fall -min 200 di set_input_delay -clock -ck -clock_fall -max 300 di |
Diagram below illustrates the way set_input_delay directives are propagated throughout the design, and where timing checks are performed.
Input to latch setup slack report is described in the slack.rep file
Path (4) : Slack of 0.762 DATA VALID: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line ____________________________________________________________________________________ 0.300 0.000 0.200 R 0.034 di di 0.498 0.198 0.310 F 0.028 (L) dff_m dff_m master ____________________________________________________________________________________ 0.498 0.198 (total) DATA REQUIRED: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line __________________________________________________________________________________ 0.000 0.000 0.200 F 0.016 (C) ck ck 0.239 0.239 0.258 R 0.046 (CK) ckn ckn inv 0.340 0.101 0.140 F 0.036 (CK) ckp ckp inv 0.260 -0.081 [INTRINSIC SETUP] 1.260 +1.000 [NEXT PERIOD] __________________________________________________________________________________ 1.260 0.260 (total) |
The value of the setup slack is given by clock_path - data_path = 1260ps - 498ps = 762ps. The intrinsic setup corresponds to an additional delay which models the amount of time required for secure memorization of the data.
Input to latch hold slack report is described in the slack.rep file
Path (2) : Slack of 0.005 DATA VALID: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line ____________________________________________________________________________________ 0.200 0.000 0.200 F 0.034 di di 0.542 0.342 0.508 R 0.028 (L) dff_m dff_m master ____________________________________________________________________________________ 0.542 0.342 (total) DATA REQUIRED: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line __________________________________________________________________________________ 0.000 0.000 0.200 F 0.016 (C) ck ck 0.239 0.239 0.258 R 0.046 (CK) ckn ckn inv 0.537 +0.298 [INTRINSIC HOLD] __________________________________________________________________________________ 0.537 0.537 (total) |
The value of the hold slack is given by data_path - clock_path = 542ps - 537ps = 5ps. The intrinsic hold corresponds to an additional delay which models the amount of time required for ensuring that the next cycle's data is not memorized in the current cycle.
Latch to latch timing checks require no additional configuration, as they are based upon the signals already propagated from inputs, and upon the clock specification. The propagation of the s.w., and corresponding timing checks are described in the following timing diagram:
Latch to latch setup slack report is described in the slack.rep file
Path (3) : Slack of 0.284 DATA VALID: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line _____________________________________________________________________________________ -0.500 0.000 0.200 R 0.016 (C) ck ck -0.399 0.101 0.128 F 0.046 (CK) ckn ckn inv -0.236 0.164 0.169 R 0.036 (CK) ckp ckp inv -0.152 0.083 0.139 F 0.028 (L) dff_m dff_m master 0.090 0.242 0.189 R 0.040 n11 n11 inv 0.321 0.231 0.305 F 0.089 (L) dff_s dff_s slave _____________________________________________________________________________________ 0.321 0.821 (total) DATA REQUIRED: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line ___________________________________________________________________________________ 0.500 0.000 0.200 R 0.016 (C) ck ck 0.601 0.101 0.128 F 0.046 (CK) ckn ckn inv 0.605 +0.005 [INTRINSIC SETUP] ___________________________________________________________________________________ 0.605 0.105 (total) |
Latch to latch hold slack report is described in the slack.rep file
Path (3) : Slack of 0.146 DATA VALID: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line ____________________________________________________________________________________ -0.500 0.000 0.200 R 0.016 (C) ck ck -0.399 0.101 0.128 F 0.046 (CK) ckn ckn inv -0.281 0.119 0.177 R 0.028 (L) dff_m dff_m master -0.223 0.057 0.088 F 0.040 n11 n11 inv 0.106 0.329 0.447 R 0.089 (L) dff_s dff_s slave ____________________________________________________________________________________ 0.106 0.606 (total) DATA REQUIRED: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line __________________________________________________________________________________ 0.500 0.000 0.200 R 0.016 (C) ck ck 0.601 0.101 0.128 F 0.046 (CK) ckn ckn inv 0.764 0.164 0.169 R 0.036 (CK) ckp ckp inv 0.960 +0.196 [INTRINSIC HOLD] -0.040 -1.000 [PREVIOUS PERIOD] __________________________________________________________________________________ -0.040 0.460 (total) |
Still based on the flip-flop design described above, the timing propagation on output t is done as follow:
In order to get setup and hold slacks on the output, one must define timing constraints on t. These timing constraints are defined with the set_output_delay SDC function. The set_output_delay specifies propagation delays from output connector to the next memory element latching the data. As a result, min and max delays are defined as shown in the diagram below.
One must also define the edge the data will be latched by. Here, dff_s is closed on the high state of ck. The data launched by t is supposed to be latched by a memory element clocked on the opposite phase, i.e. closed on low state of ck. Therefore, constraints on t should be specified relative to falling edge of ck (when dst latch closes). The set_output_delay functions should be used as follow:
set_output_delay -clock ck -clock_fall -min 200 t set_output_delay -clock ck -clock_fall -max 400 t |
Latch to output setup slack report is described in the slack.rep file
Path (1) : Slack of 0.030 DATA VALID: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line ______________________________________________________________________________ 0.000 0.000 0.200 F 0.016 (C) ck ck 0.239 0.239 0.258 R 0.046 (CK) ckn ckn inv 0.340 0.101 0.140 F 0.036 (CK) ckp ckp inv 0.568 0.227 0.327 R 0.089 (L) dff_s dff_s slave 0.570 0.003 0.118 F 0.011 (S) t t inv ______________________________________________________________________________ 0.570 0.570 (total) -> Specification: Must be stable after 0.600 |
The setup time is calculated with the maximum set_output_delay value - maximum data path - which is 400ps. As the period is 1000ps, data must arrive before time 1000 - 400 = 600ps. The setup slack is given by 600 - 570 = 30ps.
Latch to output hold slack report is described in the slack.rep file
Path (5) : Slack of 0.635 DATA VALID: Delay Acc Delta R/F Cap[pf] Type Node_Name Net_Name Line _____________________________________________________________________________ 0.000 0.000 0.200 F 0.016 (C) ck ck 0.239 0.239 0.258 R 0.046 (CK) ckn ckn inv 0.385 0.146 0.235 F 0.089 (L) dff_s dff_s slave 0.435 0.050 0.082 R 0.011 (S) t t inv _____________________________________________________________________________ 0.435 0.435 (total) -> Specification: Must be stable before -0.200 |
The hold time is calculated with the minimum set_output_delay value - minimum data path - which is 200ps. The hold slack is given by data path - clock path = 435 + 200 - 0 (the clock is ideal in the set_output_delay definition) = 635ps.