Each execution of HITAS results in the generation of a report file. This file is given the name <input_name>.rep. It contains a list of diagnostics (warnings and error messages) attributed to particular signals or transistors within the input net-list. Here we explain in more detail the particular messages which you may come across in this report file.
"[WAR] Possible unconnected supply ?" | |
Means that an internal signal whose name contains avtVddName or avtVssName has been found. Verify if this signal should be connected to an external supply, or if avtGlobalVddName and avtGlobalVssName should be positioned. | |
"[WAR] Transistor used as a resistance" | |
Indicates that a transistor P-channel (resp. N-channel) with gate connected to the ground (resp. power supply) has been found in the circuit. | |
"[WAR] Transistor used as a diode" | |
Indicates that a transistor with drain (or source) connected to gate has been found in the circuit, and the signal connecting them is neither power supply nor ground. | |
"[WAR] Transistor is always off" | |
Indicates that a transistor P-channel (resp. N-channel) with gate connected to power supply (resp. ground) has been found in the circuit. | |
"[WAR] Transistor used as a capacitance" | |
Indicates that a transistor with drain and source connected together has been found in the circuit. | |
"[WAR] Gate of transistor is not connected" | |
Indicates that a transistor gate which is connected to nothing has been found in the circuit. | |
"[WAR] Drain of transistor is not connected" | |
Indicates that a transistor drain which is connected to nothing has been found in the circuit. | |
"[WAR] Source of transistor is not connected" | |
Indicates that a transistor source which is connected to nothing has been found in the circuit. | |
"[WAR] Transistors are not used in the circuit" | |
This means that these transistors are not used to pull up or pull down any transistor gate in the circuit, or any external connector. This occurs for example if the output of a gate does not drive anything: In this case HITAS considers the transistors of the gate to be unused. | |
"[WAR] Loop between 2 gates (bleeder found)" | |
This means that a loop corresponding to a bleeder has been found in the circuit. | |
"[WAR] Loop between 2 gates (latch found)" | |
This means that a loop corresponding to a latch has been found in the circuit. | |
"[WAR] Loop between 2 gates (bi-stable found)" | |
This means that a loop corresponding to a bi-stable has been found in the circuit. | |
"[WAR] Loop between 2 gates (nothing found)" | |
This means that a two gate loop which does not correspond to a latch, bleeder or bi-stable has been found in the circuit. | |
"[WAR] Conflict may occur on signal" | |
This means that the signal may be pulled-up and pulled-down simultaneously. This is a warning since this message may disappear with a greater depth for the functional analysis process. Or it may not be possible to resolve the conflict given the logic within the circuit. | |
"[WAR] HZ state may occur on signal" | |
This means that the signal is not pulled up or pulled down for any set of input stimuli on the cone entries. This is a warning for the same reason as a conflict. | |
"[WAR] Signal does not drive anything" | |
This means that the signal is not used as the input to any gate or used to drive any external connector. | |
"[WAR] Connector unused" | |
This means that the external connector is neither the input nor the output of any of the extracted transistor gates. |
The presence of any of the following errors will disable the generation of the VHDL or Verilog description. If this behavior is not desired then HITAS must be executed with the yagleNotStrict variable.
"[ERR] Bad direction on connector" | |
Indicates that the orientation of an external connector after disassembly does not correspond to that specified in the input netlist. | |
"[ERR] Transistor gate signal is not driven" | |
Indicates that a transistor gate can not be pulled up or down. |
The following error messages will not be found in the report file. These errors are fatal and will abruptly stop the execution of HITAS.
"[FATAL] No VDD/VSS connector in the circuit" | |
This means that HITAS did not find any external ports whose name is the name of the power supply in the circuit. Do avtVddName and avtVssName have the right value? | |
"[FATAL] Connector is power supply and ground" | |
This means that HITAS found a connector whose name includes avtVddName and avtVssName. | |
"[FATAL] No VDD/VSS signal in the circuit" | |
This means that HITAS did not find any signal whose name is the name of the power supply in the circuit. | |
"[FATAL] Several external connectors on signal" | |
This means that HITAS found several external connectors connected to the same equipotential, a configuration which HITAS considers illegal. |
A global log file can be generated, logging the proccessing of all the components of the software. This file is customizable, and user can choose which component to log, and the level of log to apply.
Each line in the log file is beginning with the code related to the logged software component:
FAC | file access tracing |
MCH | disk cache tracing (used for .stm, .rcx and .spef files) |
MCC | MOSFET characterization |
RCN | RC networks construction |
TRC | RC networks characterization |
YAG | transistor netlist disassembly |
TAS | information related to delay calculation |
STM | information related to delay models |
EFG | spice deck generation |
GSP | automatic stimuli generation |
TLF | .tlf file generation |
LIB | .lib file generation |
ERR | error redirection in log file |
PRS | statistics related to netlist parsing |
SPI | detailed logging of the spice netlist and technology file parser |
The avtLogFile variable activates the creation of the log file. The avtLogEnable variable selects the software components to log and the level of log. Please refer to the 'Configuration Variables' chapter for more details.