This example intends to illustrate the VHDL optimization techniques described in the previous sections. Functional abstractions will be performed with and without timing back-annotation, in order to study the compatibility between optimizations and timing back-annotation.
The files and scripts needed for this example can be found in:
$AVT_TOOLS_DIR/tutorials/yagle/addaccu/ |
The addaccu chip consists of a four-bit adder, a four-bit register, and a 2 to 1 four-bit multiplexer.
The circuit performs an addition between either the b[3:0] and a[3:0] inputs when sel is set to 0, or between b[3:0] and the content of the four-bit register when sel is set to 1. The content of the register is overwritten by the values of the outputs s[3:0] on each falling edge of the clock, ck..
To activate inverter minimization, we just need to add the following line in the Tcl script:
avt_config yagleMinimizeInvertors yes |
The tool is invoked in the classical way:
> run.tcl |
For example, let's consider the signal s(1), in the optimized and non-optimized VHDLs:
In the non-optimized VHDL, the signal s(1) is assigned through the first chain of inverters, and through the second simple assignment in optimized VHDL (where 1981 = 259 + 768 + 533 + 421):
To activate expression simplification, we just need to add the following line in the Tcl script:
avt_config yagleSimplifyExpressions yes |
The tool is invoked in the classical way:
> run.tcl |
For example, let's consider the signal n37, in the optimized and non-optimized VHDLs:
In the non-optimized VHDL, the signal n37 is assigned by the first code line, in the optimized VHDL, the signal n37 is assigned by a more compact expression as displayed on the second code line of the example.
From the design process, we know that the chip addaccu is made up of elementary gates, such as nor, nand, xor. We also know that the names of the internal signals of those building gates are all numbers: they will be prefixed by the tool by a 'n'. If we want to retrieve the expressions of the original RTL design, it is sufficient to suppress all the expressions relative to internal signals of building gates, i.e. all the expressions built on signals beginning with a 'n'.
Signal suppression is performed by the mean of the following function:
inf_SetFigureName addaccu |
inf_DefineSuppress "n*" |
Looking at the addaccu.vhd file, we can see that the tool has retrieved the original XORs building the adder.