Package: cocotb Version: 1.2.0-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1279 Depends: python Filename: ./amd64/cocotb_1.2.0-c4m.0.0_amd64.deb Size: 199120 MD5sum: 387ae0a148f41ee3b5a65e8161489a65 SHA1: 00c082f4b3fa91330882294fc500dbd429dfc9c5 SHA256: 8df80e801fcdbf64fd04a72ecc3a204694a67084a80d1b37124e30ffffaf5505 Section: electronics Priority: extra Description: COroutine based COsimulation TestBench cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. . cocotb is completely free, open source (under the BSD License) and hosted on GitHub. . cocotb requires a simulator to simulate the RTL. Simulators that have been tested and known to work with cocotb: . Linux Platforms * Icarus Verilog * GHDL * Aldec Riviera-PRO * Synopsys VCS * Cadence Incisive * Mentor ModelSim (DE and SE) . Windows Platform * Icarus Verilog * Aldec Riviera-PRO * Mentor ModelSim (DE and SE) . https://cocotb.readthedocs.io Package: graywolf Version: 0.1.6.191014-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1243 Depends: libc6 (>= 2.29), libgsl23 (>= 2.5), libx11-6 Filename: ./amd64/graywolf_0.1.6.191014-c4m.0.0_amd64.deb Size: 421476 MD5sum: 4de59872090ea5eafdf29514d6ac9d1b SHA1: 3983bc4d0917f000af27eada371e8db42a10d460 SHA256: 34437cf65174cad6ba4c9445035f0876d4b95f3d2aad5db17aa3a911ba1e9084 Section: electronics Priority: extra Description: Standard cell placer forked from TimberWolf graywolf is used for placement in VLSI design. It's mainly used together with qflow. . http://opencircuitdesign.com/qflow/ Package: gtkwave Version: 3.3.103.dev.r1543-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 4616 Depends: libbz2-1.0, libc6 (>= 2.29), libcairo2 (>= 1.10.0), libgcc1 (>= 1:3.0), libgdk-pixbuf2.0-0 (>= 2.22.0), libglib2.0-0 (>= 2.49.3), libgtk-3-0 (>= 3.21.5), liblzma5 (>= 5.1.1alpha+20120614), libpango-1.0-0 (>= 1.14.0), libpangocairo-1.0-0 (>= 1.14.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0) Filename: ./amd64/gtkwave_3.3.103.dev.r1543-c4m.0.0_amd64.deb Size: 2381144 MD5sum: 21a6af13e762652dde2468400f537fd9 SHA1: 35a395e26df5ce702fabac5563f47d8ce6b4ba1e SHA256: 0515027839a8bee5fe6552aea3e25979c9ff4f4e67bbebc01344dd3cb6cb4805 Section: electronics Priority: extra Description: Waveform Viewer GTKWave is a waveform viewer that can view VCD files produced by most Verilog simulation tools, as well as LXT files produced by certain Verilog simulation tools. Package: iverilog Version: 11.0.dev20191104.gita621fa4-c4m.0.0 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 7 Filename: ./amd64/iverilog_11.0.dev20191104.gita621fa4-c4m.0.0_amd64.deb Size: 1208 MD5sum: e9f0efd4c1d07cc0824326970394c029 SHA1: a4c76b22ce6d060b80f8c48dc4e2bd9b7b05f8b9 SHA256: f0639e5cde55eb34abfb36892147ce52cab55a0d3ba8adf42080c93b827bded2 Section: electronics Priority: extra Description: Icarus Verilog Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. Package: magic Version: 8.2.144-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 2634 Depends: libc6 (>= 2.2.5), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0) Filename: ./amd64/magic_8.2.144-c4m.0.0_amd64.deb Size: 964984 MD5sum: d77f535d589fcd0d0b0bed4fa8e08c14 SHA1: 6bdd3fdb44830744ed41b7a078490c82a176a486 SHA256: d235cb5ac279ceb6ba008918fc23be8232a2a5e9581dd9494a49a6e82cef9c7e Section: electronics Priority: extra Description: Magic detail router for digital ASIC designs Magic detail router for digital ASIC designs . http://opencircuitdesign.com/magic/ Package: netgen-lvs Source: netgen Version: 1.5.133-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 753 Depends: libc6 (>= 2.29), libtcl8.6 (>= 8.6.0) Filename: ./amd64/netgen-lvs_1.5.133-c4m.0.0_amd64.deb Size: 191236 MD5sum: 9d55e687a651da406740bbdad7f8a91f SHA1: 70ff271f391831c8fa7741e6157f4d57795071be SHA256: ea8ddd2b59219ac47dc67fb0faaa892031e2f638738c4a27e3a45f14cd07b29b Section: electronics Priority: extra Description: Netgen complete LVS tool for comparing SPICE or verilog netlists Netgen complete LVS tool for comparing SPICE or verilog netlists . http://opencircuitdesign.com/netgen/ Package: qflow Version: 1.4.62-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 5769 Depends: libc6 (>= 2.29), yosys, graywolf, qrouter, magic, netgen-lvs Conflicts: qflow-tech-osu018, qflow-tech-osu035, qflow-tech-osu050 Filename: ./amd64/qflow_1.4.62-c4m.0.0_amd64.deb Size: 590276 MD5sum: 0b557c60562ddd323fef7826542717dd SHA1: 4567938426130f46fccaf6a54255f65b472e63a7 SHA256: a20575730cabd358059d42131cb5b60ca8d7bdd1ed14a0db3e35583ccd7837d5 Section: electronics Priority: extra Description: Qflow full end-to-end digital synthesis flow for ASIC designs Qflow full end-to-end digital synthesis flow for ASIC designs . http://opencircuitdesign.com/qflow/ Package: qrouter Version: 1.4.19-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 496 Depends: libc6 (>= 2.29), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), libx11-6 Filename: ./amd64/qrouter_1.4.19-c4m.0.0_amd64.deb Size: 166028 MD5sum: 1a2427f1291d372269f3b2101112da86 SHA1: eac838d6c70946dc249f3cf8926fc37b37240267 SHA256: b9f4c86afb6f5aa001d12428a0894cf4ab4cef83ecf24ada925de35dcc01793e Section: electronics Priority: extra Description: Qrouter detail router for digital ASIC designs Qrouter detail router for digital ASIC designs . http://opencircuitdesign.com/qrouter/ Package: verilator Version: 4.020-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 16788 Depends: libc6 (>= 2.29), libgcc1 (>= 1:3.0), libstdc++6 (>= 9) Filename: ./amd64/verilator_4.020-c4m.0.0_amd64.deb Size: 3530420 MD5sum: 86d629416956067b065811fd33c5dede SHA1: 7ab64399a60867da3566221a97cc31c2bc4eff49 SHA256: a0f3387b842ef01809b3879278dc9b742f56cb0df37262eb54a3882e286b911b Section: electronics Priority: extra Description: A fast simulator for synthesizable Verilog Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Package: yosys Version: 0.9+932-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 43041 Depends: libc6 (>= 2.29), libffi6 (>= 3.0.4), libgcc1 (>= 1:3.0), libreadline8 (>= 6.0), libstdc++6 (>= 9), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./amd64/yosys_0.9+932-c4m.0.0_amd64.deb Size: 11349176 MD5sum: bfd5c36da05ff5ec5366d6e202a656b0 SHA1: df217bd1472cc5f6def2bcee35a9af92cffcc1c4 SHA256: 33d4a24a1f48ff5c62c7d0af315cc29b79915a370479d856e0304930433a7195 Section: electronics Priority: extra Description: Yosys Open SYnthesis Suite This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. . Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. . Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). . http://www.clifford.at/yosys/